1. Field of the Invention
The present invention provides an input and output circuit of an integrated circuit chip, and more particularly, an input and output circuit with electrostatic discharge protection cells and probe pads corresponding to power rings deposited at appropriate positions of the chip, so as to increase available spaces for other probe pads, increase flexibility of power supply, and provide ESD protection.
2. Description of the Prior Art
Integrated circuits have been highly developed. Personal computers, mobile phones, digital watches, and calculators, for example, are applications of integrated circuits. With the development of semiconductor technologies, a system with multiple functions is integrated into a chip, which is called an application specific integrated circuit (ASIC), including a microprocessor, digital and analog signal processors, memories, etc. Therefore, the chip must include a plurality of input and output circuits for processing large amounts of data.
Please refer to FIG. 1, which illustrates a schematic diagram of a prior art integrated circuit chip 10. For succinctness, FIG. 1 illustrates only a corner of the chip 10. The chip 10 includes a substrate 12, a logic area 14, two input and output circuits 16, a plurality of corner wires 18, and a plurality of probe pads 20. Upon the input and output circuits 16, a plurality of power rings 22 are deposited for providing power sources. The chip 10 receives signals from a system through the probe pads 20, and transmits signals to a plurality of logic circuits (not shown in FIG. 1) in the logic area 14 through the input and output circuits 16. After performing a sequence of operations, the logic circuits in the logic area 14 transmit results to the system through the input and output circuits 16 and the probe pads 20.
For a layout of the input and output circuits 16, please refer to FIG. 2, which illustrates a schematic diagram of an input and output circuit 30 in a prior art chip. The input and output circuit 30 includes a plurality of input and output cells 32, a plurality of ESD protection and power source cell 34, a plurality of probe pads 36, and power rings 380, 382, 384, 386, 388, 390. Each input and output cell 32 receives signals from a system through the corresponding probe pad 36, and transmits signals to logic circuits of the chip for performing related operations. Conversely, the logic circuits outputs operation results to the system through the input and output cells 32 and the probe pads 36. Owing to continuous improvement in semiconductor technology, the physical area of an integrated circuit chip becomes smaller and smaller, but with more and more functions, and thus becomes more sensitive to damage from electrostatic discharge. As a result, electrostatic discharge, or ESD, protection becomes much more important, so that the input and output circuit 30 must conform to a specific rule. In FIG. 2, three ESD protection and power source cells 34 are placed between every three input and output cells 32. The ESD protection and power source cells 34 provide not only ESD protection, but also transmit power to the power rings 380, 382, 384, 386, 388, and 390 for providing power to the logic circuits inside the chip. The power rings 380, 382, 384, 386, 388, and 390 can have different voltages, and the ESD protection and power source cells 34 correspond to the voltages of the power rings 380, 382, 384, 386, 388, and 390 by turns. For example, in FIG. 2, the ESD protection and power source cells 341, 342, and 343 correspond to the power rings 380, 382, and 384, while the ESD protection and power source cells 344, 345, and 346 correspond to the power rings 386, 388, and 390. Therefore, the system can receive power from the probe pads 36 corresponding to the ESD protection and power source cells 34.
As FIG. 2 shows, in order to provide ESD protection, the ESD protection and power source cells 34 are added into the input and output circuit 30 for providing ESD protection and power supply. However, the probe pads 36 corresponding to the ESD protection and power source cells 34 (or to the input and output cells 32) which are not necessary to be used, must be bonded. For example, the ESD protection and power source cell 344 provides ESD protection, but is not necessary to provide power supply, so the probe pad 36 corresponding to the ESD protection and power source cell 344 is bonded. In short, since the input and output circuit 30 must conform to the rule for providing ESD protection, three ESD protection and power source cells 34 must be deposited for every three input and output cells 32. In this condition, available probe pads are limited, arrangement of the probe pads cannot be changed with respect to a user's requirement, and a signal to power ratio cannot be increased.
To solve the above-mentioned problem, please refer to FIG. 3, which illustrates a schematic diagram of an input and output circuit 40 of a chip. The input and output circuit 40 includes a plurality of integrated input and output cells 42, a plurality of probe pads 46, and power rings 480, 482, 484, 486, 488, and 490. Each integrated input and output cell 42 includes an input and output cell 32 and six ESD protection and power source cells 34 as shown in FIG. 2, so the integrated input and output cells 42 receive signals from a system through the corresponding probe pads 46, and transmit signals to logic circuits of the chip for performing operations. Oppositely, the logic circuits transmit results to the system through the integrated input and output cell 42 and the probe pad 46. Other than that, each integrated input and output cell 42 can provide ESD protection, and receive power from the power rings 480, 482, 484, 486, 488, and 490 for providing power to the logic circuits inside the chip or to the system outside the chip. In short, the integrated input and output cell 42 is a cell integrating the input and output cell 32 and the ESD protection and power source cells 34 shown in FIG. 2. Although the integrated input and output cells 42 can provide the functions of signal input and output, ESD protection, and power supply, each integrated input and output cell 42 occupies a large area, which is very precious in a integrated circuit. Moreover, comparing to the input and output circuit 30 in FIG. 2, there are far fewer available probe pads for the input and output circuit 40 in FIG. 3, limiting the applications.